Cpu Port Statistics - D-Link xStack DGS-3620 Series Reference Manual

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xStack DGS-3620 Series Layer 3 Managed Stackable Gigabit Switch Web UI Reference Guide
1519-2047
2048-4095
4096-9216
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Click the Apply button to accept the changes made for each individual section.
Click the Clear button to clear all statistics counters on this window.
Click the View Table link to display the information in a table rather than a line graph.
Click the View Graphic

CPU Port Statistics

To view this window, click Monitoring > Statistics > CPU Port Statistics as shown below:
including FCS octets).
The total number of packets (including bad packets) received and transmitted, that
were between 1519 and 2047 octets in length inclusive (excluding framing bits but
including FCS octets).
The total number of packets (including bad packets) received and transmitted, that
were between 2048 and 4095 octets in length inclusive (excluding framing bits but
including FCS octets).
The total number of packets (including bad packets) received and transmitted, that
were between 4096 and 9216 octets in length inclusive (excluding framing bits but
including FCS octets).
Check whether or not to display 64, 65-127, 128-255, 256-511, 512-1023, 1024-1518,
1519-1552, 1519-2047, 2048-1095 and 4096-9216 packets received and transmitted.
link to display the information in a line graph rather than a table.
Figure 12-16 CPU Port Statistics window (EI Mode Only)
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