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CDM-700 High Speed Satellite Modem
Clock Modes
8.2
CDI-10 Dual G.703 Interface
The CDI-10 Dual G.703 interface has two ports that operate independently at an E3, T3, or STS-1
data rate. A port is a Tx/Rx pair. Figure 8-2 shows the interface.
SD
Port 1
RD
SD
Port 2
RD
EXT Clk
8.2.1 CDI-10 Dual G.703 Interface Transmit Clocking
For the G.703 interface, the only clock allowed is the SD signal applied to the Tx input. Internal
Clock and Rx Loop-Timed operation do not apply to G.703 applications.
8.2.2 CDI-10 Dual G.703 Interface Receive Clocking
When the Rx Buffer is disabled, the receive clock is the Rx-Sat. In this mode, ensure the Rx
Buffer is set to minimum to reduce latency.
When the Rx Buffer is enabled, the Rx clock selections are as follows:
Rx-Sat (default)
Tx-Terr
Ext-Clk
J3
Tx
Port 1
Port 1
Rx
UNBAL
UNBAL
J2
J5
Tx
Port 2
Port 2
Rx
UNBAL
UNBAL
J4
BNC Female
5 Places
J1
External Clock
Figure 8-2. CDI-10 G.703 Dual G.703 Interface
Selecting this clock disables the Rx Buffer because the input and output
clocks are both Rx-Sat. Normally, the Rx Buffer is set for minimum when
Rx-Sat is selected.
Uses the clock from the Tx input (SD) to clock out the Rx Buffer. The Tx
and Rx data rates are the same on this interface, so asymmetrical data
rates where Tx ≠ Rx is not permitted. The two data ports are independent,
so Port 1 may have a different data rate than Port 2.
Derives a clock from a signal input to the Ext-Clk connector on the
E3/T3/STS-1 Interface Module, not J7 on the modem.
Tx PLL
Tx PLL
Rx Buffer
Rx Buffer
Rx Buffer Clk
Loopback
Tx PLL
Tx PLL
Rx Buffer
Rx Buffer
Rx Buffer Clk
Loopback
Ext
Ext
BAL
BAL
Clock
Clock
Dual E3/T3/STS-1 Card
8–3
Revision 5
MN/CDM700.IOM
Processor
Processor
Mux /
Clk
Mux /
Demux
&
Demux
Data
PLLs
PLLs
Modem
Interface
μC
Rx
Rx
Buffers
Buffers
Interface
Interface
Loopback
Loopback
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