Register; Operation - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 27 Delayed Interrupt

4.Register

4. Register
4.1 DICR:
Delayed Interrupt Control Register
This register controls to generate/clear the delayed interrupt.
• DICR: Address 0038h (Access: Byte)
7 6
– –
– –
RX/WX RX/WX
(Refer to "Meaning of Bit Attribute Symbols (Page
• Bit7-1: Undefined: Writing does not affect operation. The read value is undefined.
• Bit0: Delayed interrupt control bit
DLYI Read operation
0 No delayed interrupt request
1 Delayed interrupt request

5. Operation

Delayed interrupt service
Task A
(1) In OS, a request for task B dispatch is generated
(2) OS sets the delayed interrupt return destination (dispatch destination)
(3) OS sets the delayed interrupt (delayed interrupt generation)
(4) When OS returns, the interrupt with the highest priority sequence takes place, because an interrupt
service is prohibited in OS
(5) When the interrupt with the highest priority is completed, delayed interrupt takes place
(6) In delayed interrupt, delayed interrupt is released
(7) Returned from the delayed interrupt (dispatched to task B)
384
5 4 3
– – –
– – –
RX/
RX/WX RX/WX
WX
OS
(1)
A task dispatch request is generated.
(2)
Setting for the dispatch destination (Delay return destination)
Setting for the delay interrupt request (Generating)
(3)
2 1
– –
– –
RX/WX RX/WX
No.10)" for the attributes.)
Write operation
Delayed interrupt request clear
Delayed interrupt request generation
Preference interrupt
(5)
(4)
Delay
Delay interrupt
(6) (7)
Task B
0 bit
DLYI
0 Initial value
R/W Attribute