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Chapter 22 Main Oscillation Stabilisation Timer
3.Configuration
3. Configuration
Main clock oscillation stability wait timer
Timer operation enable
WEN
OSCR:bit 5
0
Operation stop
1
Operation enable
23-bit free run timer
0
1
2
3
Main clock
1
2
3
4
2
2 2
2
(Source oscillation)
Timer clear
WCL
OSCR:bit 2
0
Timer clear
1
Does not affect the operation
Note: Refer to
"Chapter 24 Interrupt Control (Page
290
Figure 3-1 Configuration Diagram
4
5
6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
5
6
7
8
9
10
11
12
13
14
15
2 2
2 2
2 2
2 2
2 2
2 2
Figure 3-2 List of Registers
Interval time
WS1-0
OSCR:bit 2-1
0
0
Setting disable
0
1
12
2
/
F
CL-MAIN
1
0
2
17
/
F
CL-MAIN
1
1
2
23
/ F
CL-MAIN
WIF
0
1
0
1
16
17
18
20
22
23
2
2
2
2 2
2
No.311)" for the ICR register and the interrupt vector.
WIE
OSCR:bit 6
0
Interrupt disable
1
Interrupt enable
0
OSCR:bit 7
Main clock
READ:
Without interrupt request
Oscillation stability
1
With interrupt request
wait interrupt (#46)
WRITE
Flag clear
Not affected
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