Configuration - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 24 Interrupt Control
3.Configuration

3. Configuration

The enabled interrupt request
Interrupt
request
enable bit
Interrupt
Interrupt
request
cause
flag
External interrupt ( 16)
Reload timer ( 4)
UART receive ( 4)
UART transmit ( 4)
A/D ( 2)
Real-time clock ( 1)
Main clock oscillation
stabilization timer ( 1)
Timebase timer ( 1)
Clock timer ( 1)
Up/down counter ( 2)
PPG ( 3)
Free-run Timer ( 2)
Input capture ( 2)
Output compare ( 4)
Delayed interrupt ( 1)
Reserved for system [REALOS] ( 2)
INT instruction ( 176)
Interrupt control (CPU side)
Interrupt level mask register
ILM (4-0) -0) -0) ILM register in CPU
00000
l
System processing
01111
10000
l
Interrupt processing
11110
11111
Interrupt level [ICRxx: ICR (4-0)]
Interrupt
control
Interrupt number (#)
circuit
312
Figure 3-1 Configuration Diagram
Priority judging circuit
NMI processing
Interrupt priority
judging circuit
Interrupt control register
ICR (4-0)
00000
01111
10000
11110
11111
Figure 3-2 Configuration Diagram
The inside of the CPU
Rewrite
Prioritization
Initial level
Interrupt number (#) x 4 + TBR
Interrupt level
/interrupt
number
HLDREQ
generator
cancel
request
ICR0-ICR47: bit4-0
Cannot be set.
Higher interrupt
Lower interrupt
Disable interrupts
SSP SSP
I flag
0
Disable
1
Enable
Table base register
TBR Initial value: FFC00
Vector table
Address
NMI
Wakeup
Level
To the CPU
HALT
Number
RAM
( ( PS, PC)
PS
PC
(1k Bytes)