Table of Contents
Advertisement
Chapter 37 Output Compare
3.Configuration Diagram
3. Configuration Diagram
Output Compare 0-1
Compare register 0
OCCP0
IVF
TCCS2: bit6
0
0 Overflow not present
Overflow present
1
1
Free-run timer 2
TCDT2
CLR TCCS2:bit2
0
0
No effect
1
Clear
Compare register 0
OCCP1
Note: For information about ICR registers and interrupt vectors, see
No.311)".
760
Figure 3-1 Configuration Diagram
CST 0
OCS01: bit0
0
0
Disable compare operation
1
Enable compare operation
Com-
pare
0
Match -> Latch
0
reversal
1
0
1
Com-
OR
pare
1
CST 1
OCS01: bit1
0
0
Disable compare operation
1
Enable compare operation
T CCS0 : bit 3
MODE
0
0
No clear on compare-match
1
Clear on compare-match
Figure 3-2 Register List
ICE0 OCS01: bit4
0
0
Disable interrupts
1
Enable interrupts
ICP0 OCS01: bit6
0
0
Interrupt request not present
1
Interrupt request present
Write 0: Flag clear
External clock (for free-run timer 2)
General-use port read
OT D0 OCS01: bit8
0
0
Low fixed
1
High fixed
0
0
* Compare operation only
1
writable when stopped
From general-use
port register
Latch
CMOD
OCS01: bit12
0
OCCP1 match alone inverts OP1 latch.
1
OCCP0 or OCCP1 match inverts OP1 latch.
Match -> Latch reversal
Latch
From general-use
port register
OT D1 OCS01: bit9
0
0
0
0
Low fixed 1c
1
1
1
High fixed
* Compare operation only
writable when stopped
General-use port read
External clock (for free-run timer 2)
0
ICP1
OCS01: bit 7
0
0
1
Interrupt request not present
1
Interrupt request present
Write 0: Flag clear
ICE1 OCS01: bit5
0
0
Disable interrupts
1
Enable interrupts
OCU0 Interrupt (#100)
PFR15.0
General-use Port
OUT0
0
OCU0/TOT0/P15.0
1
OCU1/TOT1/P15.1
0
PFR15.1
General-use Port
OUT1
OCU1 Interrupt (#100)
"Chapter 24
Interrupt Control (Page
Advertisement
Table of Contents
