6. Settings
Table 6-1 Settings for Operating at 1/2 of the Main Clock
Setting
Clock source selection
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings for Operating Using the Main PLL
Setting
Main PLL operation enable
Clock source selection
*: For the setting procedure, refer to the section indicated by the number.
Table 6-3 Settings for Operating Using the Subclock
Setting
Subclock selection enable
Clock source selection
*: For the setting procedure, refer to the section indicated by the number.
Table 6-4 Settings for Selecting the Division Ratio for the Operating Clocks
Setting
Clock source selection
Operating clock division ratio selection
*: For the setting procedure, refer to the section indicated by the number.
Setting register
Clock source control register (CLKR)
Setting register
Clock source control register (CLKR)
Setting register
Clock source control register (CLKR)
Setting register
Clock source control register (CLKR)
Operating clock division setting registers
(DIVR0, DIVR1)
Chapter 13 Clock Control
6.Settings
Setting
procedure*
See 7.3
Setting
procedure*
See 7.1
See 7.3
Setting
procedure*
See 7.1
See 7.3
Setting
procedure*
See 7.3
See 7.4
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