Configuration - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 13 Clock Control
3.Configuration
• External bus clock (CLKT): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16
The clock used by the external bus expansion interface. The circuits that use this clock are as follows.
• External bus expansion interface
• External CLK output

3. Configuration

PLL1EN
0
1
OSCDS 1
0
1
X0 Main clock
source
(F
X1 CLK-MAIN
X0A
( F
X1A
SCKEN
0
1
OSCD2
0
1
OSCD1
0
1
190
Figure 3-1 Configuration Diagram
Set PLL multiplier
CLKR: bit2
Halt PLL
PLLDIVM: bit5-0
Enable (start) PLL
PLLDIVN: bit5-0
Set PLL autogear
OSCCR: bit0
Main clock continues to
PLLDIVG: bit5-0
run in subclock mode
PLLMULG: bit7-0
Main clock halts in
subclock mode
PLL
)
Divide by 2
Subclock
source
)
CLK-SUB
CLKS1-
CLKR: bit3
CLKS0
Main clock divided by 2
Subclock selection prohibited 00
Subclock selection enabled
Main clock divided by 2
01
STCR: bit1
10
Continue oscillation in stop mode
11
Halt oscillation in stop mode
STCR: bit0
Continue oscillation in stop mode
Halt oscillation in stop mode
Figure 3-2 Register List
B3-B0
DIV R0: bit 7-4
0000 No division
0001
Divide by 2
0010
Divide by 3
0011
Divide by 4
0100
Divide by 5
0101
Divide by 6
0110
Divide by 7
0111
Divide by 8
1000-1110 Divide by 9-15
1111
Divide by 16
Divider
Divider
Base
clock
(φ)
P3-P0
Permitted
CLKR: bit6-4
change
00=>01, 10
(main clock mode)
01=>11, 00
(main clock mode)
Main PLL
10=>00
(main clock mode)
1000-1110
Subclock
11=>01
(subclock mode)
T3-T0
DIV R1: bit 7-4
0000
No division
0001
Divide by 2
0010
Divide by 3
0011
Divide by 4
0100
Divide by 5
0101
Divide by 6
0110
Divide by 7
0111
Divide by 8
1000-1110 Divide by 9-15
1111
Divide by 16
CPU clock
(F )
CLKB
Peripheral clock
(F )
CLKP
External bus clock
Divider
(F (F ) )
CLKT CLKT
Base clock
(φ)
DIV R1: bit3-0
0000 No division
0001
Divide by 2
0010
Divide by 3
0011
Divide by 4
0100 Divide by 5
0101
Divide by 6
0110
Divide by 7
0111 Divide by 8
Divide by 9-15
1111
Divide by 16