Condition Code Register (Ccr) - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

3.2.1

Condition Code Register (CCR)

The condition code register (CCR) located in the lower 8 bits of the program status (PS)
consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and
the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the
CPU accepts interrupt requests.
I Structure of condition code register (CCR)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
R4 R3
PS
X: Indeterminate
- : Unused
I Arithmetic operation result bits
G
Half-carry flag (H)
Set to "1" when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an arithmetic
operation. Clear to "0" otherwise. As this flag is for the decimal adjustment instructions, do not use this flag
in cases other than addition or subtraction.
G
Negative flag (N)
Set to "1" if the most significant bit (MSB) is set to "1" as a result of an arithmetic operation. Clear to "0"
when the bit is set to "0".
G
Zero flag (Z)
Set to "1" when an arithmetic operation results in "0". Clear to "0" otherwise.
G
Overflow flag (V)
Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Clear to "0" if the
overflow does not occur.
Figure 3.2-2 Structure of condition code register
RP
R2 R1 R0 — — —
Half-carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
CCR
H I IL1 IL0 N Z
CHAPTER 3 CPU
Bit 1 Bit 0
CCR initial value
V C
X011XXXX
B
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