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Chapter 6 EIT: Exceptions, Interrupts and Traps
5.EIT Interrupt Level
5. EIT Interrupt Level
Interrupt level is between 0 and 31, and controlled with 5 bits.
Table 5-1 Interrupt Level of EIT
Level
Binary
Decimal
00000
0
...
...
...
...
00011
3
00100
4
00101
5
...
...
...
...
01110
14
01111
15
10000
16
10001
17
...
...
...
...
11110
30
11111
31
Only 16 through 31 levels are operable.
Undefined-instruction exception, coprocessor absent trap, coprocessor error trap and INT instruction are not
affected by interrupt level. Also, ILM is not changed by interrupt level.
6. EIT Vector Table
For EIT vector table, see the chapter of
Vector for EIT is between address which table-base register [TBR] indicates and a 1 kByte area.
Its size is 4 bytes per one vector. For vector number/vector address/trigger, see
(Page
No.73)".
Address arithmetic is as follows.
Vector address = [TBR] + Offset value = [TBR] + {03FC
Lower two bits as the result of addition are always used for "00".
000FFC00
through 000FFFFF
H
If you rewrite the TBR value, the mode and reset vectors always use the fixed address of 000FFFF8
000FFFFC
.
H
122
Description
(Reserved for system)
...
...
(Reserved for system)
INTE instruction
Step trace trap
(Reserved for system)
...
...
(Reserved for system)
NMI (for users)
Interrupt
Interrupt
...
...
Interrupt
N/A
"3. Interrupt Vector Table (Page
areas are initial values of vector table by reset.
H
Remarks
If original value of ILM is between 16 and 31, these
values are not configurable to ILM by program.
When ILM is set, user Interrupt is disabled.
When ICR is set, Interrupt is disabled.
No.73)".
- 4 x Vector number (No.)}
H
"3. Interrupt Vector Table
,
H
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