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Chapter 9 Reset
6.Watchdog Reset (INIT: Settings Initialization Reset)
6. Watchdog Reset (INIT: Settings Initialization Reset)
6.1 Trigger
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a
watchdog reset request is generated unless "A5
delay register (WPR) within the time specified by the watchdog period selection bits
(RSRR.WT[1:0]).
6.2 Releasing the Reset Request
The watchdog reset request invokes a settings initialization reset (INIT). The watchdog reset
request is released after the request is received and the settings initialization reset (INIT)
generated, or when an operation reset (RST) occurs.
6.3 Flag
When watchdog reset request triggers a settings initialization reset (INIT), the watchdog timeout
flag (RSRR.WDOG) is set to "1".
6.4 Reset Level
This reset has the maximum reset level and initializes all settings. This type of reset is called the
settings initialization reset (INIT).
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the
oscillation stabilization time elapses.
6.5 Initialization Triggered by Watchdog Reset (INIT)
Same as for a reset triggered by an INIT pin input.
However, the oscillation stabilization time selection bits (STCR.OS[1:0]) and reset cause flags
(INIT, WDOG, SRST) are not initialized and retain their existing values.
6.6 Reset Cancellation Sequence
Same as for INIT pin input.
(See
"Chapter 20 Software Watchdog Timer (Page
148
" and "5A
" are written to the watchdog reset
H
H
No.273)" for details.)
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