Chapter 13 Clock Control; Overview; Features - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 13 Clock Control

1. Overview

The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator.
The circuit supports a range of clock speeds from the high speed clock (100MHz maximum) to the low speed
clock (32.768kHz).
Source oscillation
Main clock
(source oscillation)
Sub clock
(source oscillation)

2. Features

■ Source oscillation
• Main clock (F
CL-MAIN
Input from the X0/X1 pins and used as the high speed clock
• Subclock (F
CL-SUB
Input from the X0A/X1A pins and used as the low speed clock
• Subclock (F
CL-SUB
RC oscillator and used as the low speed clock
■ Base clock (F): Selectable from 3 different clocks
• Main PLL (programmable) : F
• Main clock divided by 2
• Subclock
■ Operating clocks: Selectable from 16 different speeds
• CPU clock (CLKB): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16
The clock used by the CPU, internal memory, and internal buses. The circuits that use this clock are as
follows.
• CPU, internal RAM, internal ROM, bit search module,
• I bus, D bus, F bus, X bus
• On-chip debug support unit (DSU)
• Peripheral clock (CLKP): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16
The clock used by the peripheral functions and peripheral bus. The circuits that use this clock are as
follows.
• Peripheral bus
• Clock controller (bus interface unit only)
• Interrupt controller
• I/O ports
• External interrupt inputs, UART, 16-bit timer, and similar peripheral functions
Base clock generator
Divide by 2
PLL
): 4MHz
): 32.768kHz
): 100kHz
x (MxN)\M
CL-MAIN
: F divided by 2
CL-MAIN
: F
CL-SUB
Operating clock generator
Divider
Divider
Selector
Divider
Chapter 13 Clock Control
CPU clock
Peripheral clock
External bus clock
Base clock
1.Overview
189