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Chapter 23 Sub Oscillation Stabilisation Timer
3.Configuration
3. Configuration
Clock timer
Clock timer
(14-bit free run timer)
0
0
1
1
2
2
3
3
Sub-clock
1
2
3
4
2
2
2
2
(Source oscillation)
32.768 kHz
Timer clear
WCL
0
Timer clear
1
Does not affect the operation
Note: For the ICR register and interrupt vector, refer to
300
Figure 3-1 Configuration Diagram
4
4
5
5
6 7
6 7
8
8
9 10 11 12 13 14
9 10 11 12 13 14
5
6
7
8
9
10
11
12
13
14
2
2
2
2
2
2
2
2
2
2
WPCR:bit 2
Figure 3-2 List of Registers
Interval time
WS1-0
WPCR:bit 2-1
2
10
/ F
0
0
CL-SUB
0
1
2
13
/ F
CL-SUB
1
0
14
2
/ F
CL-SUB
2
15
/ F
1
1
CL-SUB
0
1
WRITE; 0: Flag clear
15
2
"Chapter 24 Interrupt Control (Page
WIE
WPCR:bit 6
0
Interrupt disable
1
Interrupt enable
0
WIF
WPCR:bit 7
Clock timer
Without interrupt request
Interrupt (#49)
With interrupt request
1
No.311)".
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