Registers - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 38 Reload Timer

4.Registers

4. Registers
4.1 TMCSR: Reload Timer Control Status Register
The control status register controls the operation mode of the reload timer and interrupts.
• TMCSR0 (Reload timer 0): Address: 001B6H (Access:
• TMCSR1 (Reload timer 1): Address: 001BEH (Access:
• TMCSR2 (Reload timer 2): Address: 001C6H (Access:
• TMCSR3 (Reload timer 3): Address: 001CEH (Access:
• TMCSR4 (Reload timer 4): Address: 001D6H (Access:
• TMCSR5 (Reload timer 5): Address: 001DEH (Access:
• TMCSR6 (Reload timer 6): Address: 001E6H (Access:
• TMCSR7 (Reload timer 7): Address: 001EEH (Access:
15 14
– –
- -
RX/WX RX/WX RX/WX
× ×
7 6
MOD0 – OULT
0 -
R/W RX/WX
×
–
(O: can be rewritten, x: cannot be rewritten)
(For information on attributes, see
• bit15-14: Undefined
Writing has no effect on the operation. The read value is "0".
• bit13: Undefined (reload timer 0 - reload timer 2)
Always write "0". The read value is "0".
• bit12-10: Count clock selection
CSL2 CSL1
0 0
0 0
0 1
0 1
1 0
1 1
Notes: Depending on whether an internal clock or an external event is selected, the meaning of
the operation mode selection bit (MOD[2:0]) changes.
778
13 12 11
– CSL2 CSL1
- 0 0
R0/WX R/W
× × ×
5 4 3
RELD INTE
0 0 0
R/W R/W R/W
× × ×
"Meaning of Bit Attribute Symbols (Page
CSL0 Count clock
0 Internal clock CLKP/2
1 Internal clock CLKP/8
0 Internal clock CLKP/32
1 External event (external clock)
1 Internal clock CLKP/64
0 Internal clock CLKP/128
Byte, Half-word
Byte, Half-word
Byte, Half-word
Byte, Half-word
Byte, Half-word
Byte, Half-word
Byte, Half-word
Byte, Half-word
10 9
CSL0 MOD2 MOD1
0 0
R/W R/W0 R/W
× ×
2 1
UF CNTE TRG
0 0
R(RM1),W R/W R0/W
Ο Ο
CLKP: peripheral clock
)
)
)
)
)
)
)
)
8 bit
0 Initial Value
Attribute
Rewrite during
×
operation
0 bit
0 Initial Value
Attribute
Rewrite during
Ο
operation
No.10)".)
Remarks