Configuration - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 41 Up/Down Counter
3.Configuration

3. Configuration

Up/Down Counter 0 (8 Bit Mode)
8 bit mode
M16E UDCC0 : bit15
0 0
8 bit mode
CMS1-0
0 0 0 0
0 0 1 1
1 0 1 0
1 1 1 1
Peripheral clock
Prescaler
CLKP
CLKS
From port data
0 0
register
1 1
P20 EPFR20.0
0 0
Others
1 Enable UDC
AIN0/SIN2/P20.0
BIN0/SOT2/P20.1
P20 EPFR20.1
CES1-0 UDCC0: bit 9-8
0 Others
1 0 0 0
Enable UDC Read
from
0
port
1 0
1 1
From port data
register
ZIN0/SCK2/P20.2
P20 EPFR20.2
0 0 Others
1 Enable UDC
836
Figure 3-1 Configuration Diagram
CDCF
UDCC0: bit14
0 No change direction
Direction changed
1
WRITE 0: Flag clear
- UDCC0: bit11 -10 -
Timer mode (Countdown only)
Up/down count mode
CSTR
Phase difference count mode (Multiply by 2)
0 Stop counting
Phase difference count mode (Multiply by 4) 1
Start counting
Activation
UDCC0: bit 12
CLKP divided by 2
Counter clear
CLKP divided by 8
CTUT UDCC0: bit6
0 No impact
Read from port
1 Data transfer
* Only 16 bit transfer is enabled
while counting stops.
Edge
detection
OR
Gate
Reload/compare register (Write only)
0
Disable edge detection
1
Enable falling edge detection
Enable rising edge detection UDCLR UDCC0: bit2
Enable both edge detection 0
1
Read from
port
Edge
detection
CGE1-0
0 0
0
From port data
1
register
1
CFIE
UDCC0: bit 13
0 0 Disable interrupts
1
Enable interrupts
0
1
UDF1-0 - UDCS0: bit 1-0 -
Write: Disabled, Read only
0 0 0 0
No input
0 0 1
Countdown
1 0 0
UDCS0: bit7 Countup
1 1
Both countdown and countup
Up/Down Counter (Read only)
UDCR0
1
Reload
0
RLDE UDCC0: bit4
0 Disable reload
Enable reload
1
UDRC0
Clear
Disabling
UDCC0: bit1-0, bit 2
CGSC
0: Counter clear function 1: Gate function
0 0
Disable edge detection Disable level detection
1
Enable falling edge detection Enable LOW level detection
0
Enable rising edge detection Enable HIGH level detection
1
Disable setting Disable setting
UDC0 interrupt
OR
(#128)
UDIE
UDCS0: bit5
0 Disable interrupts
OVFF
UDCS0: bit3
1
Enable interrupts
0 No overflow
1
Overflowed
WRITE 0: Flag clear
1
OR
UDFF
UDCS0: bit2
0
No underflow
0
1
Underflowed
WRITE 0: Flag clear
0
CMPF
UDCS0: bit4
Com-
0
Compare match
pare
1
1
No compare match
WRITE 0: Flag clear
CITE
UDCS0: bit6
0 Disable interrupts
1 Enable interrupts
0
1
UCRE UDCC0:bit5
0
Disable counter clear
1 Enable counter clear