Chapter 12 Instruction Cache; General Description; Main Body Structure - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 12 Instruction Cache

This chapter describes the instruction cache memory included in MB91460 family members and
its operation.

1. General description

The instruction cache is a fast local memory for temporary storage. Once an instruction is
accessed to be fetched from external slower memory, the instruction cache holds the instruction
code inside to increase the speed of accessing the same code from then on. The instruction
cache data RAM and tag RAM are made directly read/write-accessible by software by setting the
RAM mode. To turn off the instruction cache after turning it on once, be sure to use the
subroutine shown in Section 4.2.4 "Settings for handling the I-Cache".

2. Main body structure

• FR basic instruction length:
• Block arrangement system:
• Block
4 bytes
Way 1
Cache tag
128 Blocks
Cache tag
Way 2
Cache tag
128 Blocks
Cache tag
2 bytes
2-way set associative system
128 blocks per way
16 bytes per block (= 4 sub-blocks)
4 bytes per sub-block (= 1 bus access unit)
Figure 2-1 Instruction Cache Structure
4 bytes 4 bytes
I3
Sub-block 3 Sub-block 2
Sub-block 3 Sub-block 2
Sub-block 3 Sub-block 2
Sub-block 3 Sub-block 2
4 bytes
I2 I1
Sub-block 1
Sub-block 1
Sub-block 1
Sub-block 1
Chapter 12 Instruction Cache
1.General description
4 bytes
I0
Sub-block 0 Block 0
Sub-block 0 Block 127
Sub-block 0 Block 0
Sub-block 0 Block 127
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