Memory Protection - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 29 MPU / EDSU
3.Break Functions
On break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operand
break exception routine.
Table 3-5 Operand address and data value break combinations
EP3/2 EP1/0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1

3.5 Memory Protection

Due to the availability of address range comparators for the operand and instruction addresses the wish is obvios,
to use the same comparator hardware as a memory protection unit (MPU).
Following table list the possible type configurations and its feasibility to be used for memory protection. The number
of break points and MPU channels is valid for 8 comparator groups implemented.
Table 3-6 Comparator Type Configuration
CTC CMP1 Input
00 IA
01 OA
10 OA
11 OA
Additional to the given hardware there were made some extensions to provide the user with a more likely configu-
ration of read, write and execute permissions instead of the more bus applicable definition of the operand break size
and type definitions OBS/OBT, including read-modify-write. With the introduction of the SuperVisor mode a defini-
tion of User and SuperVisor permissions is possible.
404
COMB
0 No break detection
0 Independent data break (match value on any operand address)
0 Independent Operand break (match operand address)
0 Independent Data break and Operand break
1 No break detection
1 No break detection
1 No break detection
1 Data value break (match both operand address and value)
CMP0 Input
IA
OA
IA
DT
Function
Max. Break Points
(MPE=0)
32 Instruction breaks
32 Operand breaks
16 + 16 IA/OA breaks
16 data value breaks
Max. MPU Channels
(MPE=1)
16 ranges with execute
permissions
16 ranges with read/
write permissions
8 ranges with read/
write and execute per-
missions or 8+8 inde-
pendent ranges
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