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Chapter 12 Instruction Cache
4.Cacheable areas in the instruction cache
● Cache Entry Update
Cache entries are updated as shown in the following table.
Hit
Miss
4. Cacheable areas in the instruction cache
•
The instruction cache can cache data only in external bus space.
•
Even when the contents of external memory are updated by DMA transfer, the instruction
cache does not refresh its contents to be coherent with the new contents of the memory. In
this case, flush the cache to give it coherence.
•
Each chip select area can be set as a non-cacheable area. The penalty for this is one cycle
compared to the cache off state. (See Section 5.5 "Setting Chip Select Areas" in Chapter 5
"EXTERNAL INTERFACE".)
5. Settings for handling the I-Cache
1)
Initializing
To use the I-Cache, first, clear the cache contents. Erase the old data by setting the register
FLUSH bit and ELKR bit to 1.
Idi #0x000003e7,r0
Idi #0B00000110,r1
stb r1,@r0
The cache is now initialized.
2)
Enabling (turning ON) cache
To enable the I-Cache, set the ENAB bit to 1.
Idi #0x000003e7,r0
Idi #0B00000001,r1
stb r1,@r0
All subsequently-accessed instructions will be cached.
Cache can be validated and initialized at the same time.
Idi #0x000003e7,r0
Idi #0B00000111,r1
stb r1,@r0
3)
Disabling (turning OFF) cache
186
Unlock
Not updated
The memory data is loaded, and the
cache entry data is updated.
Lock
Not updated.
Not updated at tag miss.
Updated when sub-block invalid.
// I-Cache control register address
// FLUSH bit (bit 1)
// ELKR bit (bit 2)
// Writing to register
// I-Cache control register address
// ENAB bit (bit 0)
// Writing to register
// I-Cache control register address
// ENAB bit (bit 0)
// FLUSH bit (bit 1)
// ELKR bit (bit 2)
// Writing to register
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