Recommended Settings - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 14 PLL Interface

5.Recommended Settings

5. Recommended Settings
PLL Input
(CK)
[MHz]
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
• Important remark: Not all settings which are shown in this table are available for all devices. Please consult
the available datasheet for each device for the maximum allowed PLL output and the allowed maximum
frequencies for each clock domain (CLKB, CLKP and CLKT) respectively.
212
Frequency Parameter Clockgear Parameter
DIVM DIVN
2 25
2 24
2 23
2 22
2 21
2 20
2 19
2 18
2 17
2 16
2 15
2 14
2 13
2 12
2 11
4 10
4 9
4 8
4 7
6 6
8 5
10 4
12 3
PLL Output
(X)
DIVG MULG
[MHz]
16 24
16 24
16 24
16 24
16 20
16 20
16 20
16 20
16 16
16 16
16 16
16 16
16 12
16 12
16 12
16 24
16 24
16 24
16 24
16 24
16 28
16 32
16 32
Core base
Clock
[MHz]
200 100
192 96
184 92
176 88
168 84
160 80
152 76
144 72
136 68
128 64
120 60
112 56
104 52
96 48
88 44
160 40
144 36
128 32
112 28
144 24
160 20
160 16
144 12