Register - Fujitsu MB91460 SERIES FR60 User Manual

4. Register

4.1 WPCRH: Sub oscillation stabilisation timer Control Register
This register is used to select interval time, clear the timer, control interrupt, control timer stop etc., and
confirm the states.
• WPCRH: Address 04CAh (Access: Byte)
7 6
WIF WIE
0 0
R(RM1),W R/W
(For the attributes, refer to
(Refer to "8. Caution (Page
• Bit7: Sub oscillation stabilisation timer interrupt request flag
WIF Read Operation
0 Without interrupt request
1 With interrupt request
• The sub oscillation stabilisation timer interrupt request flag bit is set to "1" at the falling edge of the
selected interval period output.
• Bit6: Interrupt request enable
WIE
0
1
• If the interrupt request enable bit is set to "1" an interrupt request is enabled.
• If the sub oscillation stabilisation timer interrupt request flag is (WIF="1"), and if the interrupt request
enable bit (WIE) is set to "1", an interrupt request is immediately generated.
• Bit5: Timer operation enable
WEN
0
1
• Bit4-3: Reserved bit Be sure to write "0". The read value is "0".
• Bit2-1: Interval period selection
WS1 WS0
0 0 2
0 1
2
1 0
2
1 1
2
• Bit0: Timer clear
WCL
0
1
• The timer is also cleared by INITX terminal input and watchdog reset.
Notes 1: Initial value can be set using the setting initialization reset (INIT terminal input,
5 4 3
WEN – –
0 X X
R/W RX/W0 RX/W0
"Meaning of Bit Attribute Symbols (Page
No.309)".)
Interrupt request is prohibited
Interval period (F
10
/F (31.25ms)
CL-SUB
13
/F (0.25s)
CL-SUB
14
/F (0.50s)
CL-SUB
15
/F (1.00s)
CL-SUB
Clears the sub oscillation stabilisation timer.
Writing does not affect write operation.
2 1
WS1 WS0
0 0
R/W R/W
No.10)".)
Write Operation
Clears the interrupt request flag
Writing does not affect operation
Operation
Interrupt request enable
Operation
Stops timer operation
Enables timer operation
= 32.768kHz)
CL-SUB
Operation
Chapter 23 Sub Oscillation Stabilisation Timer
0 bit
WCL
1 Initial value (At INIT) *1
R1,W Attribute
4.Register
301