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Chapter 4 CPU Architecture
2.Features
2. Features
■ Features of internal architecture
• RISC architecture
• Base instruction: 1 instruction/1 cycle
• 32-bit architecture
• General-purpose register: 32-bit x 16
• 4GB of linear memory space
• Equipped with multiplier.
•32-bit x 32-bit multiplication: 5 cycles
•16-bit x 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
•High-speed respond (6 cycles)
•Support of multiple interrupts
•Level mask function (16 levels)
• Enhanced instruction for I/O operation
•Transfer instruction between memories
•Bit-processing instruction
• Highly efficient code
• Length of base instruction words: 16 bits
• Standby mode (Low power consumption mode)
• Sleep/Stop
• Setting function of clock division ratios
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