Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 595

Cp1h/cp1l cpu unit
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Double-precision Floating-point Instructions
Precautions
3-15-20 DOUBLE EXPONENTIAL POWER: PWRD(860)
Purpose
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
562
Name
Label
Underflow Flag
UF
Negative Flag
N
The source data in words S to S+3 must be in IEEE754 floating-point data for-
mat.
Raises a double-precision (64-bit) floating-point number to the power of
another double-precision (64-bit) floating-point number.
PWRD(860)
B
B: First base word
E: First exponent word
E
D: First destination word
D
Variations
Executed Each Cycle for ON Condition
Executed Once for Upward Differentiation
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification
Block program areas
OK
OK
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
Indirect DM addresses
in binary
Indirect DM addresses
in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
Operation
Unchanged
ON if the result is negative.
OFF in all other cases.
Step program areas
Subroutines
OK
B
CIO 0 to CIO 6140
W0 to W508
H0 to H508
A0 to A956
T0000 to T4092
C0000 to C4092
D0 to D32764
@ D0 to @ D32767
*D0 to *D32767
---
---
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Section 3-15
PWRD(860)
@PWRD(860)
Not supported.
Interrupt tasks
OK
E
D
A448 to A956

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