Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 731

Interrupt Control Instructions
Operand Specifications
Description
Flags
Precautions
Examples
698
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
Indirect DM addresses
in binary
Indirect DM addresses
in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
The value of N identifies the interrupt.
Input Interrupts: N = 100 to 107, 110 to 117, or 6 to 13
The mask status or the trigger specification (ON or OFF) specified with N is
stored in D.
Scheduled Interrupt: N = 4 or 14
The scheduled interrupt interval (set value) or the present value of the internal
timer specified with N is stored in D as a hexadecimal value. The units for the
scheduled interrupt interval is specified in the PLC Setup as the Scheduled
Interrupt Interval.
Name Label
Error Flag ER
MSKR(692) can be executed in the main program or in interrupt tasks.
Input Interrupts
When W0.00 turns ON in the following example, the mask status of input
interrupt 0 (CIO 0.00) is stored in D100. The value in the example (0003) says
that the interrupt is unmasked in incrementing counter mode.
W0.00
MSKR
N 100
D100
D
N
---
---
---
---
---
---
---
---
---
Specified values only
---
---
---
Operation
ON if N is not within the specified range of 0 to 5 (0 to 15
for the CJ1M).
OFF in all other cases.
15
D100 0 0
Section 3-19
D
CIO 0 to CIO 6143
W0 to W511
H0 to H511
A448 to A959
T0000 to T4095
C0000 to C4095
D0 to D32767
@ D0 to @ D32767
*D0 to *D32767
---
DR0 to DR15
,IR0 to ,IR15
–2048 to +2047, IR0 to
–2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15
8 7 0
0 3