Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 282

Cp1h/cp1l cpu unit
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Data Movement Instructions
Variations
Applicable Program Areas
Operand Specifications
Description
Flags
Variations
Executed Each Cycle for ON Condition
Executed Once for Upward Differentiation
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification
Block program areas
OK
OK
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
Indirect DM addresses
in binary
Indirect DM addresses
in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
MVN(022) inverts the bits in S and transfers the result to D. The content of S
is left unchanged.
Source word
Name
Label
Error Flag
ER
Equals Flag
=
Negative Flag
N
Step program areas
Subroutines
OK
S
CIO 0 to CIO 6143
W0 to W511
H0 to H511
A0 to A959
T0000 to T4095
C0000 to C4095
D0 to D32767
@ D0 to @ D32767
*D0 to *D32767
#0000 to #FFFF (binary)
DR0 to DR15
---
,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15
Bit status
inverted.
Operation
OFF
ON if the content of D is 0000 after execution.
OFF in all other cases.
ON if the leftmost bit of D is 1 after execution.
OFF in all other cases.
Section 3-7
MVN(022)
@MVN(022)
Not supported
Interrupt tasks
OK
D
A448 to A959
---
Destination word
249

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