Figure 13.5.4B When Setting '0' On Wdbc (Master Side Of Master Transmission) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

16-bit microcontrollers
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2. When setting '0' on WDBC (Master side of master transmission)
Frist Frame
DataN-3(04H)
COM
DERR
Read
N
DEER
DEWR
Write
DEWR
Trans.
Buffer
WDB
Write
07H, 06H, 05H, 04H, 04H, 03H, 02H, 01H, 00H
WDB
WDBC
WDBE
WDBF
Note : N = N bytes transmission.
The figure inside ()is the transmission data.

Figure 13.5.4b When setting '0' on WDBC (Master side of master transmission)

MB90580 Series
DataN-2(03H)
Start
Multi-Add
Can read the rest of the transmission bytes
N
03H
Second Frame
Master- Add
Slave-Add
Control
Telegraph bytes
02H
Write DERR value
FFH, FEH, FDH, FCH, FBH
As data is left from 3 bytes before,
write transmission data 5 bytes
Write until WDB becomes full
13.5 Operation
DataN-1(02H)
DataN(01H)
Transmission data left is 0
Transmit the rest of 2 bytes
02H
01H
02H
Transmit the previous
frame's data
WEDBF=0 due to1 byte transmission
Chapter 13: IE Bus
00H
187

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