Registers And Register Details; Clock Output Enable Register (Clkr); Figure 19.3A Registers Of Clock Monitor Function - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

19.3 Registers and Register Details

19.3 Registers and Register Details
Clock Output Enable Register
Address : 00003E
Read/write
Initial value

19.3.1 Clock output enable register (CLKR)

Address : 00003E
Read/write
Initial value
[bit 3] : CKEN
CKOT output enable bit.
Ordinary port
0
CKOT output
1
[bits 2, 1, and 0] FRQ2, FRQ1, and FRQ0
These bits are used to select the clock output frequency.
FRQ2 FRQ1
0
0
0
0
1
1
1
1
268 Chapter 19: Clock Monitor Function
7 6
— —
H
(-) (-)
(-) (-)

Figure 19.3a Registers of Clock Monitor Function

7 6
— —
H
(-) (-)
(-) (-)
FRQ0 Output clock
∅/2
0 0
∅/2
0 1
∅/2
1 0
∅/2
1 1
∅/2
0 0
∅/2
0 1
∅/2
1 0
∅/2
1 1
5 4 3
— —
CKEN
(-) (-) (R/W)
(-) (-) (0)
5 4 3
— —
CKEN
(-) (-) (R/W)
(-) (-) (0)
∅=16 MHz
1
125 ns
2
250 ns
3
500 ns
1 µs
4
2 µs
5
4 µs
6
8 µs
7
16 µs
8
2 1 0
FRQ2 FRQ1 FRQ0
(R/W) (R/W) (R/W)
(0) (0) (0)
2 1 0
FRQ2 FRQ1 FRQ0
(R/W) (R/W) (R/W)
(0) (0) (0)
∅=8 MHz ∅=4 MHz
250 ns 500 ns
1 µs
500 ns
1 µs 2 µs
2 µs 4 µs
4 µs 8 µs
8 µs 16 µs
16 µs 32 µs
32 µs 64 µs
MB90580 Series
Bit number
CLKR
Bit number
CLKR