Timing Diagram Of Multiple Frame Transmission; Figure 13.5.4A When Setting '1' On Wdbc (Master Side Of Master Transmission) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

16-bit microcontrollers
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13.5 Operation

13.5.4 Timing Diagram of Multiple Frame Transmission

1. When setting '1' on WDBC (Master side of master transmission)
Frist Frame
DataN-3(04H)
COM
DERR
Read
DEER
DEWR
Write
DEWR
Trans.
Buffer
WDB
Write
WDB
WDBC
WDBE
WDBF
Note : N = N bytes transmission.
The number inside () is the transmission data.

Figure 13.5.4a When setting '1' on WDBC (Master side of master transmission)

186
Chapter 13: IE Bus
DataN-2(03H)
Start
Can read the rest of the transmission byte
N
N
07H, 06H, 05H, 04H, 04H, 03H, 02H, 01H, 00H
WDB is empty as WDBC=1
Second Frame
Multi-Add
Master- Add
Slave-Add
02H
03H
Control Telegraph bytes DataN-1(FFH) DataN(FEH)
Transmission data left is 0
Write DERR value
Transmit the rest of 2 bytes
02H
FEH
Transmit the data newly set
FFH, FEH, FDH, FCH, FBH, FAH, F9H
Write the transmission data 8 bytes
WEDBF=0 due to1 byte transmission
Write until WDB becomes full
MB90580 Series
00H
FEH

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