Figure 13.3B Registers Of Ie Bus (2/3) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.3 Registers and Register Details
Mutliaddress, control bit set register (DCWR)
Address: 000075
H
Read/write
Initial value
Telegraph length set register (DEWR)
Address: 000074
H
Read/write
(R/W)
Initial value
Status register upper byte (STRH)
Address: 000079
H
Read/write
Initial value
Status register lower byte (STRL)
Address: 000078
H
Read/write
Initial value
Lock read register (LRRH, LRRL)
Address: 00007B
H
Reserved Reserved
Read/write
Initial value
Address: 00007A
H
LD07
Read/write
Initial value
144 Chapter 13: IE Bus
15 14 13
DO3 DO2 DO1
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
DE7 DE6 DE5
(R/W) (R/W)
(0) (0) (0)
15 14 13
COM TE PEF
(R) (R/W) (R)
(0) (0) (X)
7 6 5
WDBF RDBF WDBE
(R) (R) (R)
(0) (0) (1)
15 14 13
Reserved
(R)
(R)
(R/W)
(1) (1)
(1)
7 6 5
LD06 LD05
(R) (R)
(R)
(X) (X)
(X)

Figure 13.3b Registers of IE BUS (2/3)

12 11 10
DO0 C3 C2
(R/W) (R/W)
(R/W)
(0) (0)
(0)
4 3 2
DE4 DE3 DE2
(R/W) (R/W)
(R/W)
(0) (0)
(0)
12 11 10
ACK RIF TIF
(R) (R/W) (R/W)
(X) (0)
(0)
4 3 2
RDBE ST3 ST2
(R)
(R) (R)
(1)
(X) (X)
12 11 10
LOC LD11 LD10
(R)
(R) (R)
(X)
(0) (X)
4 3 2
LD04 LD03 LD02
(R) (R)
(R)
(X) (X)
(X)
9 8
Bit Number
C1 C0 DCWR
(R/W) (R/W)
(0) (0)
Bit Number
1 0
DE1 DE0 DECR
(R/W) (R/W)
(0) (0)
9 8 Bit Number
TSL EOD STRH
(R) (R)
(0) (0)
Bit Number
1 0
ST1 ST0 STRL
(R) (R)
(X) (X)
9 8
Bit Number
LD09 LD08 LRRH
(R)
(R)
(X)
(X)
Bit Number
1 0
LD01 LD00 LRRL
(R)
(R)
(X)
(X)
MB90580 Series