Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 301

[bits 7 and 6] ICP1 and ICP0
These bits are used as output compare interrupt flags. '1' is written to these bits when the compare reg-
ister value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are
enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set. These bits are
cleared by writing '0.'
Writing '1' has no effect. '1' is always read by a read-modify-write instruction.
* ICP1: Corresponds to output compare 1/3 ICP0: Corresponds to output compare 0/2
[bits 5 and 4] ICE1 and ICE0
These bits are used as output compare interrupt enable flags. While the '1' is written to these bits, an
output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.
* ICE1: Corresponds to output compare 1/3 ICE0: Corresponds to output compare 0/2
[bits 3 and 2] Unused bits
[bits 1 and 0] CST1 and CST0
The*se bits are used to enable the comparison with 16-bit free-run timer.
Ensure that a value is written to the compare register before the compare operation is enabled.
* CST1: Corresponds to output compare 1/3 CST0: Corresponds to output compare 0/2
Note: Since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit
free-run timer stops compare operation.
MB90580 Series
0 No compare match (default)
1 Compare match
Output compare interrupt disabled
0
(default)
1 Output compare interrupt enabled
0 Compare operation disabled (default)
1 Compare operation enabled
20.3 Registers and Register Details
Chapter 20: 16-Bit I/O Timer 281