Operation; Iebus Control - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.5 Operation

13.5 Operation

13.5.1 IEBus control

(1) Master transmit
The unit is set as master transmit to transmit data to the slave by sending data/command control bits as
AH, BH, EH or FH. The sequences for operating in master transmit are described as below:
1. The master address is written in unit address register (MAWH, MAWL), the slave address is written in
slave address register (SAWH, SAWL), multiaddress bit and control bits are written into multiaddress,
control bit set register (DCWR). After that, the command register (CMRH) is set to release
communication inhibit mode.
2. When the master has won the arbitration (after the master address field is finished), the state code (0H)
indicating start of transmission is set in ST3-0 of status register (STRL) and transmit interrupt occurs. At
this time, the number of transmitted data byte is required to write into telegraph length set register
(DEWR) and transmit data is set in write data buffer (WDB), unless the WDb is not full.
3. When one byte of data is transmitted, the number of data in WDB is deducted by one. According to the
setting of TIT1, TIT0 in command register (CMRL) that control the interval for writing data in WDB, the
transmit interrupt occurs. At that time, the state code equals '1H' indicating data transmission and WDB
is not full. Therefore, data should be written in WDB.
4. If the specified number of data or command has been transmitted correctly, the state code (2H)
indicating transmission ends normally is set in ST3-0 of status register (STRL), the EOD bit in STRH is
set and transmit interrupt occurs.
5. If error occurs during transmission or in multi-frame communication the number of data byte specified in
telegraph bit set register (DEWR) cannot be transmitted completely, the state code (3H) indicating
transmission ends without all data are transmitted is set in ST3-0, and transmit interrupt occurs. At this
time, the content of communication error can be known by checking the status of TSL, PEF, TE in
status register (STRH).
When timing error is occurred during the transmission, the data stored in WDB can't be transmitted. If the
TE bit is cleared and re-transnit sequence is executed, those data left in WDB, excluding the data byte
that has timing error will be re-transmit. In order to perform new data transmission, the bit WDBC in CMRL
must be written '1' to clear the write data buffer.
(2) Slave transmit
Data transmit
This mode is set when the master sends control bits either 3H or 7H to slave and requests it to transmit
data back to the master. The sequences for operating in slave data transmit are described as below:
1. After receiving master control code 3H or 7H, the data code (0H) indicating transmit start is set to
ST3-0 of status register and the transmit interrupt is occurred. At this time, set the telegraph length set
register (DEWR) with the nunmber of byte of data which are required to be transmitted. The transmit
data can be written to WDB, provided that WDB is not full.
2. During the start of telegraph field transmission, the status register bits ST3-0 are set to 1H indicating
data transmission in progress and transmit interrupt occurs. At that moment, transmit data can be
written to the WDB, provided that WDB is not full.
3. When one byte of data is transmitted, the number of data in WDB is deducted by one. According to the
setting of TIT1, TIT0 in command register (CMRL) that control the timing for writing data in WDB, the
transmit interrupt occurs. Data can be written in WDB if state code is still (1H) and WDB is not full.
4. If the specified number of data or command has been transmitted correctly, the state code (2H)
indicating transmission ends normally is set in ST3-0 of status register (STRL), the EOD bit in STRH is
set and transmit interrupt occurs.
174 Chapter 13: IE Bus MB90580 Series