Table 13.3.2D Internal Clock Frequency - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

[bit 3, 2] CS1, CS0 (Cycle select):
These bits control both the CPU internal clock cycle and IEBUS controller clock cycle and CS1 and CS0
must be set to '0'. .
CS1
0
0
1
1
Note1:
The CPU and IEBus internal clock frequency are calculated by the above equation provided
that the CPU operating frequency is inside the guaranteed range.
The accuracy of clock cycle calculation for mode 0 and 1 is ±1.5%, and for mode 2 is ±0.5%.
Note2:
[bit 1] RDBC (Read data buffer clear):
This bit is used to clear the 8-byte read data buffer, RDB. When this bit is set to '1', all the eight bytes in
RDB are cleared. (RDBE = 1)
This bit is always read as '0'.
[bit 0] WDBC (Write data buffer clear):
This bit is used to clear the 8-byte write data buffer, WDB. When this bit is set to '1', all the eight bytes
in WDB are cleared and WDB becomes empty (WDBE = 1 )
This bit is alwarys read as '0'.
For the communication with no. of byte transfer greater than the maximum transfer byte per frame, the
data written in the previous frame will no longer valid if '1' is written to this bit. The data written in the
current frame will be transmitted first. In converse, if '0' is written to this bit, the unsent data in the pre-
vious frame will be prioritized to be sent first.
If the transmission is terminated due to timing error, even thought '0' is written to this bit, the transmis-
sion will be started from the next data and not the last one which has not been sent completely.
MB90580 Series

Table 13.3.2d Internal clock frequency

CPU internal clock φ
CS0
12MHz (12.58 MHz)
0
1 Setting inhibited
0 Setting inhibited
1 Setting inhibited
13.3 Registers and Register Details
IEBus internal
clock
6MHz(6.29MHz)
----
----
----
Equation
φ = φ/2
ΙΕ
----
----
----
Chapter 13: IE Bus 149