Wdtc (Watch-Dog Timer Control Register); Table 5.3.1A Reset Cause Registers - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

5.3 Registers and register details

5.3.1 WDTC (Watch-Dog Timer Control Register)

Watch-Dog timer control register
Address : 0000A8
Read/write
Initial value
Don't use read-modify-write command to access this register, otherwise malfunction will occur.
[bits 7 to 3] PONR, STBR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table 5.3.1a.
All bits are cleared to '0' after the WDTC register is read. The WDTC register is a read-only register.
This is a read-only register. Note that during power-on only, the contents of the bits that indicate
sources other than power-on are not guaranteed. Therefore, software should be designed to ignore the
other bits when the PONR bit is "1".
Reset cause
Power-on
Hardware standby
Watch-dog timer
External pin
RST bit
(*: The previous value is maintained.)
[bit 2] WTE
While the watch-dog timer is stopped, writing '0' to this bit activates the watch-dog timer. Subsequently,
writing '0' clears the watch-dog timer counter. Writing '1' has no effect.
The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog timer. '1' is
always read from this bit.
[Bits 1, 0] WT1, WT0
These bits select the watchdog interval time. Only the data written when the watchdog timer is started
up is valid. Data written to these bits at any time other than watchdog startup is ignored. Note that the
clock that is input to the watchdog timer is selected according to the result of ANDing the WDCS bit of
the WTC and the SCM bit of the LPMCR. In other words, if WDCS is set to "1", then the timebase timer
output can be selected if the main clock and the PLL clock are selected, and the watch timer
can be selected if the subclock is selected.
The interval time settings are shown in Table 5.3.1a.
These bits are write-only bits.
54 Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions
7 6 5
H
PONR STBR WRST
(R) (R) (R)
(X) (X) (X)

Table 5.3.1a Reset cause registers

PONR
1
*
*
*
*
4 3 2
ERST SRST WTE
(R) (R) (W)
(X) (X) (1)
STBR WRST
— —
1 *
* 1
* *
* *
Bit number
1 0
WT1 WT0
WDTC
(W) (W)
(1) (1)
ERST SRST
— —
* *
* *
1 *
* 1
MB90580 Series
output