Xilinx Virtex-6 FPGA User Manual page 95

Table 3-12: TX Pattern Generator Attributes (Cont'd)
Attribute
PCS_RESET_LANE0
PCS_RESET_LANE1
PCS_RESET_LANE2
PCS_RESET_LANE3
PCS_RESET_1_LANE0
PCS_RESET_1_LANE1
PCS_RESET_1_LANE2
PCS_RESET_1_LANE3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Type
16-bit Hex This attribute controls the datapath resets. It varies by mode:
64B/66B: 0xF3FE
8B/10B: 0xFC5B
Raw: 0xFF3B
PRBS: 0xFFCE
Default: 0xFFFF
[15:12]: Reserved
[11]: Reset 64B/66B receive
[10]: Reset 64B/66B transmit
[9]: Reset 8B/10B receive
[8]: Reset 8B/10B transmit
[7]: Reset RX FIFO
[6]: Reset RX raw shift pointer
[5]: Reset PRBS checker
[4]: Reset PRBS generator
[3]: Reserved
[2]: Reset TX FIFO
[1]: Reset RX loopback FIFO
[0]: Reserved
16-bit Hex [15:2]: Reserved. Use the recommended values from the Virtex-6 FPGA
GTH Transceiver Wizard.
[1:0]: This attribute controls the datapath resets. It varies by mode:
64B/66B: 2'b10
8B/10B: 2'b00
Raw: 2'b00
PRBS: 2'b10
Default: 2'b11
www.xilinx.com
TX Pattern Generator
Description
95