Xilinx Virtex-6 FPGA User Manual page 17

Table 1-3: GTH Quad Port Summary (Cont'd)
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Port
RXCTRL0[7:0]
RXCTRL1[7:0]
RXCTRL2[7:0]
RXCTRL3[7:0]
RXCTRLACK0
RXCTRLACK1
RXCTRLACK2
RXCTRLACK3
RXDATA0[63:0]
RXDATA1[63:0]
RXDATA2[63:0]
RXDATA3[63:0]
RXDISPERR0[7:0]
RXDISPERR1[7:0]
RXDISPERR2[7:0]
RXDISPERR3[7:0]
RXENCOMMADET0
RXENCOMMADET1
RXENCOMMADET2
RXENCOMMADET3
RXN0
RXN1
RXN2
RXN3
RXP0
RXP1
RXP2
RXP3
RXPOLARITY0
RXPOLARITY1
RXPOLARITY2
RXPOLARITY3
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Port and Attribute Summary
Dir Clock Domain
RXUSERCLKIN0
RXUSERCLKIN1
Out
RXUSERCLKIN2
RXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
Out
TXUSERCLKIN2
TXUSERCLKIN3
RXUSERCLKIN0
RXUSERCLKIN1
Out
RXUSERCLKIN2
RXUSERCLKIN3
RXUSERCLKIN0
RXUSERCLKIN1
Out
RXUSERCLKIN2
RXUSERCLKIN3
RXUSERCLKIN0
RXUSERCLKIN1
In
RXUSERCLKIN2
RXUSERCLKIN3
In (Pad) RX Serial Clock
RXUSERCLKIN0
RXUSERCLKIN1
In
RXUSERCLKIN2
RXUSERCLKIN3
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