Xilinx Virtex-6 FPGA User Manual page 19

Table 1-3: GTH Quad Port Summary (Cont'd)
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Port
TXBUFRESET0
TXBUFRESET1
TXBUFRESET2
TXBUFRESET3
TXCTRL0[7:0]
TXCTRL1[7:0]
TXCTRL2[7:0]
TXCTRL3[7:0]
TXCTRLACK0
TXCTRLACK1
TXCTRLACK2
TXCTRLACK3
TXDATA0[63:0]
TXDATA1[63:0]
TXDATA2[63:0]
TXDATA3[63:0]
TXDATAMSB0[7:0]
TXDATAMSB1[7:0]
TXDATAMSB2[7:0]
TXDATAMSB3[7:0]
TXDEEMPH0
TXDEEMPH1
TXDEEMPH2
TXDEEMPH3
TXMARGIN0[2:0]
TXMARGIN1[2:0]
TXMARGIN2[2:0]
TXMARGIN3[2:0]
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Port and Attribute Summary
Dir Clock Domain
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
Out
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
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