Xilinx Virtex-6 FPGA User Manual page 51

X-Ref Target - Figure 2-5
QUAD
PLL
RECCLK0
CDR0
RECCLK1
CDR1
RECCLK2
CDR2
RECCLK3
CDR3
PMA Block
Figure 2-5: TX and RX Parallel Clock Dividers in the PCS Block
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Quad
TX
Common TX
PCS
Clock
PCS Clock
Divider for
GTH Quad
PLLPCSCLKDIV[5:0]
RX PCS Clock
Divider 0
SIPO_Data_Width0
RX PCS Clock
Divider 1
SIPO_Data_Width1
RX PCS Clock
Divider 2
SIPO_Data_Width2
RX PCS Clock
Divider 3
Lane 3
SIPO_Data_Width3
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TX Lane PCS
Clock Divider
TX PCS
Clock for
Lane 0
SAMPLERATE0[2:0]
RX PCS Clock for Lane 0
Lane 0
TX Lane PCS
Clock Divider
TX PCS
Clock for
Lane 1
SAMPLERATE1[2:0]
RX PCS Clock for Lane 1
Lane 1
TX Lane PCS
Clock Divider
TX PCS
Clock for
Lane 2
SAMPLERATE2[2:0]
RX PCS Clock for Lane 2
Lane 2
TX Lane PCS
Clock Divider
TX PCS
Clock for
Lane 3
SAMPLERATE3[2:0]
RX PCS Clock for Lane 3
TX Fabric
TXUSERCLK0
Clock Divider
TX_FABRIC_WIDTH0
RX_FABRIC_WIDTH0
RX Fabric
RXUSERCLK0
Clock Divider
TX Fabric
TXUSERCLK1
Clock Divider
TX_FABRIC_WIDTH1
RX_FABRIC_WIDTH1
RX Fabric
RXUSERCLK1
Clock Divider
TX Fabric
TXUSERCLK2
Clock Divider
TX_FABRIC_WIDTH2
RX_FABRIC_WIDTH2
RX Fabric
RXUSERCLK2
Clock Divider
TX Fabric
TXUSERCLK3
Clock Divider
TX_FABRIC_WIDTH3
RX_FABRIC_WIDTH3
RX Fabric
RXUSERCLK3
Clock Divider
UG371_c2_16_020210
PLL
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