Xilinx Virtex-6 FPGA User Manual page 18

Chapter 1: Transceiver and Tool Overview
Table 1-3: GTH Quad Port Summary (Cont'd)
18
Port
RXPOWERDOWN0[1:0]
RXPOWERDOWN1[1:0]
RXPOWERDOWN2[1:0]
RXPOWERDOWN3[1:0]
RXRATE0[1:0]
RXRATE1[1:0]
RXRATE2[1:0]
RXRATE3[1:0]
RXSLIP0
RXSLIP1
RXSLIP2
RXSLIP3
RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
RXUSERCLKOUT0
RXUSERCLKOUT1
RXUSERCLKOUT2
RXUSERCLKOUT3
RXVALID0[7:0]
RXVALID1[7:0]
RXVALID2[7:0]
RXVALID3[7:0]
SAMPLERATE0[2:0]
SAMPLERATE1[2:0]
SAMPLERATE2[2:0]
SAMPLERATE3[2:0]
TSTPATH
TSTREFCLKFAB
TSTREFCLKOUT
www.xilinx.com
Dir Clock Domain
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
RXUSERCLKIN0
RXUSERCLKIN1
In
RXUSERCLKIN2
RXUSERCLKIN3
In
Out
RXUSERCLKIN0
RXUSERCLKIN1
Out
RXUSERCLKIN2
RXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
Out Async
Out
Out
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
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