Xilinx Virtex-6 FPGA User Manual page 16

Chapter 1: Transceiver and Tool Overview
Table 1-3: GTH Quad Port Summary (Cont'd)
16
Port
DRDY
DWE
GTHINIT
GTHINITDONE
GTHRESET
GTHX2LANE01
GTHX2LANE23
GTHX4LANE
MGMTPCSLANESEL[3:0]
MGMTPCSMMDADDR[4:0]
MGMTPCSRDACK
MGMTPCSRDDATA[15:0]
MGMTPCSREGADDR[15:0]
MGMTPCSREGRD
MGMTPCSREGWR
MGMTPCSWRDATA[15:0]
PLLPCSCLKDIV[5:0]
PLLREFCLKSEL[2:0]
POWERDOWN0
POWERDOWN1
POWERDOWN2
POWERDOWN3
REFCLK
RXBUFRESET0
RXBUFRESET1
RXBUFRESET2
RXBUFRESET3
RXCODEERR0[7:0]
RXCODEERR1[7:0]
RXCODEERR2[7:0]
RXCODEERR3[7:0]
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Dir Clock Domain
Out DCLK
In DCLK
In DCLK
Out DCLK
In Async
In Async
In Async
In Async
In DCLK
In DCLK
Out DCLK
Out DCLK
In DCLK
In DCLK
In DCLK
In DCLK
In DCLK
In DCLK
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
In
RXUSERCLKIN0
RXUSERCLKIN1
In
RXUSERCLKIN2
RXUSERCLKIN3
RXUSERCLKIN0
RXUSERCLKIN1
Out
RXUSERCLKIN2
RXUSERCLKIN3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
N/A