Xilinx Virtex-6 FPGA User Manual page 47

X-Ref Target - Figure 2-3
These rules must be observed when sharing a reference clock to ensure that jitter margins
for high-speed designs are met:
1.
2.
3.
4.
5.
6.
The maximum number of GTH transceivers that can be sourced by a single clock pin pair
is 12.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
MGTREFCLKP
I
MGTREFCLKN
IB
Figure 2-3: Multiple GTHE1_QUADs with Shared Reference Clock
The sharing of a reference clock is allowed only for 2.8 Gb/s and below.
The external reference clock that drives the REFCLK input port of a given quad (the
sourcing GTH Quad) needs to be used by the PLL in the same Quad due to the position
of the REFCLK multiplexer.
The number of GTH Quads above the sourcing GTH Quad must not exceed one.
The number of GTH Quads below the sourcing GTH Quad must not exceed one.
The reference clock cannot be routed across the FPGA to the other GTH Quad column.
The reference clock cannot be shared with a neighboring GTX transceiver.
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Reference Clock Distribution and Selection
Tied Off
REFCLK
REFCLK
O
REFCLK
Tied Off
Float
GTHE1_QUAD
OFF
0
PLL
GTHE1_QUAD
OFF
0
PLL
GTHE1_QUAD
OFF
0
PLL
Float
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