Xilinx Virtex-6 FPGA User Manual page 84

Chapter 3: Transmitter
Table 3-6: TX 8B/10B Block Attributes (Cont'd)
Attribute
PCS_RESET_LANE0
PCS_RESET_LANE1
PCS_RESET_LANE2
PCS_RESET_LANE3
PCS_RESET_1_LANE0
PCS_RESET_1_LANE1
PCS_RESET_1_LANE2
PCS_RESET_1_LANE3
TX_FABRIC_WIDTH0
TX_FABRIC_WIDTH1
TX_FABRIC_WIDTH2
TX_FABRIC_WIDTH3
84
Type
16-bit Hex This attribute controls the datapath resets. It varies by mode:
64B/66B: 0xF3FE
8B/10B: 0xFC5B
Raw: 0xFF3B
PRBS: 0xFFCE
Default: 0xFFFF
[15:12]: Reserved
[11]: Reset 64B/66B receive
[10]: Reset 64B/66B transmit
[9]: Reset 8B/10B receive
[8]: Reset 8B/10B transmit
[7]: Reset RX FIFO
[6]: Reset RX Raw FIFO
[5]: Reset PRBS checker
[4]: Reset PRBS generator
[3]: Reserved
[2]: Reset 8B/10B TX FIFO
[1]: Reset RX loopback FIFO
[0]: Reset 64B/66B and PRBS TX FIFO
16-bit Hex [15:2]: Reserved. Use the recommended values from theVirtex-6
FPGA GTH Transceiver Wizard.
[1:0]: This attribute controls the datapath resets. It varies by mode:
64B/66B: 2'b10
8B/10B: 2'b00
Raw: 2'b00
PRBS: 2'b10
Default: 2'b11
Integer This attribute sets the mapping of the internal data width (PCS) to
the external data width (fabric) for the transmitter. Valid settings
are:
" 16 " (DRP value 3'b000): PCS to Fabric 1:1
" 20 " (DRP value 3'b000): PCS to Fabric 1:1
" 32 " (DRP value 3'b011): PCS to Fabric 1:2 32 bits
" 40 " (DRP value 3'b101): PCS to Fabric 1:2 40 bits
" 64 " (DRP value 3'b010): PCS to Fabric 1:4 64 bits
" 80 " (DRP value 3'b110): PCS to Fabric 1:4 80 bits
" 6466 " (DRP value 3'b111): 64B/66B mode
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010