Xilinx Virtex-6 FPGA User Manual page 12
Gth transceivers
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Also See for Virtex-6 FPGA:
- Manual (381 pages) ,
- User manual (317 pages) ,
- Getting started manual (77 pages)
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Chapter 1: Transceiver and Tool Overview
X-Ref Target - Figure 1-1
GTHE1_QUAD
Column
GTHE1_
QUAD_
X1Y2
GTHE1_
QUAD_
X1Y1
GTHE1_
QUAD_
X1Y0
GTXE1
Column
GTXE1_
X1Y11
GTXE1_
X1Y10
GTXE1_
X1Y9
GTXE1_
X1Y8
GTXE1_
X1Y7
GTXE1_
X1Y6
GTXE1_
X1Y5
GTXE1_
X1Y4
GTXE1_
X1Y3
GTXE1_
X1Y2
GTXE1_
X1Y1
GTXE1_
X1Y0
Figure 1-1: GTH Transceiver Inside the Virtex-6 XC6VHX255T FPGA
Notes relevant to
1.
2.
12
I/O
Collumn
Configuration
Figure
1-1:
This figure does not illustrate exact size, location, or scale of the functional blocks to
each other. It does show the correct number of available resources.
To improve clarity, this figure does not show the CLB, DSP, and block RAM columns.
www.xilinx.com
MMCM
MMCM
MMCM
MMCM
MMCM
MMCM
I/O
Collumn
MMCM
MMCM
PCI
Express
MMCM
Ethernet
MAC
MMCM
Ethernet
MAC
MMCM
PCI
MMCM
Express
Virtex-6 FPGA GTH Transceivers User Guide
GTHE1_QUAD
Column
GTHE1_
QUAD_
X0Y2
GTHE1_
QUAD_
X0Y1
GTHE1_
QUAD_
X0Y0
GTXE1
Column
GTXE1_
X0Y11
GTXE1_
X0Y10
GTXE1_
X0Y9
GTXE1_
X0Y8
GTXE1_
X0Y7
GTXE1_
X0Y6
GTXE1_
X0Y5
GTXE1_
X0Y4
GTXE1_
X0Y3
GTXE1_
X0Y2
GTXE1_
X0Y1
GTXE1_
X0Y0
UG371_c1_01_082109
UG371 (v2.0) February 16, 2010
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