Xilinx Virtex-6 FPGA User Manual page 20

Chapter 1: Transceiver and Tool Overview
Table 1-3: GTH Quad Port Summary (Cont'd)
The ports in
Table 1-4: GTH Reference Clock (IBUFDS_GTHE1) Port Summary
20
Port
TXN0
TXN1
TXN2
TXN3
TXP0
TXP1
TXP2
TXP3
TXPOWERDOWN0[1:0]
TXPOWERDOWN1[1:0]
TXPOWERDOWN2[1:0]
TXPOWERDOWN3[1:0]
TXRATE0[1:0]
TXRATE1[1:0]
TXRATE2[1:0]
TXRATE3[1:0]
TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKOUT0
TXUSERCLKOUT1
TXUSERCLKOUT2
TXUSERCLKOUT3
Table 1-4 are part of the GTH IBUFDS primitive.
Port
I
IB
O
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Dir Clock Domain
Out
TX Serial Clock
(Pad)
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
TXUSERCLKIN0
TXUSERCLKIN1
In
TXUSERCLKIN2
TXUSERCLKIN3
In
Out
Dir Clock Domain
In
In
Out
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
N/A
N/A
Async
Async
Async