Xilinx Virtex-6 FPGA User Manual page 79

Table 3-4
Table 3-4: FPGA TX Interface Attributes
Attribute
BUFFER_CONFIG_LANE0
BUFFER_CONFIG_LANE1
BUFFER_CONFIG_LANE2
BUFFER_CONFIG_LANE3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
defines the FPGA TX interface attributes.
Type
16-bit Hex This attribute defaults to 16'h4004.
[15:4]: TX_BUFFER_CONFIG[11:0] read pointer adjustment for TX
buffer in the data converter.
• For auto adjustment mode, TX_BUFFER_CONFIG[11:0] =
12'h400.
• For manual adjustment mode, TX_BUFFER_CONFIG[11:0] settings
depend on TX_FABRIC_WIDTH and if the GTH transceivers
within a Quad are configured as a x4 link (GTHX4LANE = 1'b1):
• x4 (GTHX4LANE = 1'b1): [TX_FABRIC_WIDTH] = [TX_BUFFER_CONFIG]
"16" or "20" (DRP value 3'b000): 12'h0A4
"32" (DRP value 3'b011): 12'h394
"40" (DRP value 3'b101): 12'h394
"64" (DRP value 3'b010): 12'h250
"80" (DRP value 3'b110): 12'h250
"6466" (DRP value 3'b111): 12'h0A4
•
x1 (GTHX4LANE = 1'b0): [TX_FABRIC_WIDTH] = [TX_BUFFER_CONFIG]
"16" or "20" (DRP value 3'b000): 12'h23C
"32" (DRP value 3'b011): 12'h0E8
"40" (DRP value 3'b101): 12'h0E8
"64" (DRP value 3'b010): 12'h3A8
"80" (DRP value 3'b110): 12'h3A8
"6466" (DRP value 3'b111): 12'h23C
[4:0]: RX_BUFFER_CONFIG[3:0] read pointer adjustment for RX
buffer in the data converter.
• For auto adjustment mode, RX_BUFFER_CONFIG[3:0] = 0100.
• For manual adjustment mode, RX_BUFFER_CONFIG[3:0] settings
depend on the RX_FABRIC_WIDTH:
[RX_FABRIC_WIDTH] = [RX_BUFFER_CONFIG]
"16" or "20" (DRP value 3'b000): 4'b0001
"32" (DRP value 3'b011): 4'b0000
"40" (DRP value 3'b101): 4'b0000
"64" (DRP value 3'b010): 4'b0000
"80" (DRP value 3'b110): 4'b0000
"6466" (DRP value 3'b111): 4'b0001
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FPGA TX Interface
Description
79