Xilinx Virtex-6 FPGA User Manual page 57

Table 2-10: Reset Ports (Cont'd)
Port
RXCTRLACK0
RXCTRLACK1
RXCTRLACK2
RXCTRLACK3
RXPOWERDOWN0[1:0]
RXPOWERDOWN1[1:0]
RXPOWERDOWN2[1:0]
RXPOWERDOWN3[1:0]
RXRATE0[1:0]
RXRATE1[1:0]
RXRATE2[1:0]
RXRATE3[1:0]
RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
SAMPLERATE0[2:0]
SAMPLERATE1[2:0]
SAMPLERATE2[2:0]
SAMPLERATE3[2:0]
TXBUFRESET0
TXBUFRESET1
TXBUFRESET2
TXBUFRESET3
TXCTRLACK0
TXCTRLACK1
TXCTRLACK2
TXCTRLACK3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Dir Clock Domain
Out TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In N/A
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
Out TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
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Description
Assertion of this acknowledgment signal indicates
completion of a change event on RXRATE<n> and
RXPOWERDOWN<n>.
The state of this port is valid only after GTHINITDONE is
driven High and TXUSERCLKIN<n> is stable.
This control signal requests the receiver power state:
00: Normal operation.
10: Power off receiver logic. The PLL continues to
operate in this state.
This port must always be set to 2'b10 during initialization
and when GTHRESET is asserted.
If the Quad is configured as a x4 link, only the port from
Lane 0 is valid.
This control signal specifies the receiver lane divider values:
00: Full data rate
10: 1/4 data rate
All other encodings are reserved.
This port is active after the TX side becomes active.
TXUSERCLKIN<n> must be stable to use this port.
This port must always be set to 2'b00 during initialization
and when GTHRESET is asserted.
This port provides a clock for the internal receiver PCS
datapath. It is a buffered version of RXUSERCLKOUT<n>.
This control signal specifies the frequency of the strobe
signal relative to the internal transmitter PCS clock after the
transmitter lane dividers:
000: Full rate
010: 1/4 rate
All other encodings are reserved.
This port must always be set to 3'b000 during
initialization and when GTHRESET is asserted.
This input resets the buffer inside the TX data converter (see
Figure 3-2, page 81). Both the internal TX clock and
TXUSERCLKIN<n> must be stable before a reset can be
applied to the buffer.
This acknowledgment signal indicates completion of a
change event on TXRATE<n>, SAMPLERATE<n>, and
TXPOWERDOWN<n>.
The state of this port is valid only after the GTHINITDONE
is driven High and TXUSERCLKIN<n> is stable.
Reset and Initialization
57