Xilinx Virtex-6 FPGA User Manual page 64

Chapter 2: Shared Transceiver Features
6.
7.
8.
9.
10. Change SAMPLERATE<n>[2:0] to the value used for the application and wait for
11. Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.
12. Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.
13. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.
14. Change RXRATE<n>[1:0] to the value used for the application and wait for
15. Change RXPOWERDOWN<n>[1:0] to 2'b00.
16. Wait for RXCTRLACK<n> to go High.
17. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for
X-Ref Target - Figure 2-9
GTHINIT
GTHINITDONE
TXRATE <n>[1:0]
SAMPLERATE<n>[2:0]
TXPOWERDOWN<n>[1:0]
TXBUFRESET<n>
TXCTRLACK<n>
RXRATE<n>[1:0]
RXPOWERDOWN<n>[1:0]
RXCTRLACK<n>
RXBUFRESET<n>
Figure 2-9: GTH Transceiver Reset when in Divided Line Rate Mode
Notes relevant to
1.
2.
64
Assert GTHRESET for 1 DCLK clock cycle. TXCTRLACK<n> and RXCTRLACK<n>
from all four lanes are asserted.
Wait for TXCTRLACK<n> and RXCTRLACK<n> from all four lanes to be deasserted
and then assert GTHINIT for 1 DCLK clock cycle.
Wait for GTHINITDONE to go High. The PLL is locked after GTHINITDONE is
asserted.
Change TXRATE<n>[1:0] to the value used for the application and wait for
TXCTRLACK to go High.
TXCTRLACK to go High.
RXCTRLACK signal to go High.
normal operation.
2'b00
3'b000
2'b10
(1)
2'b00
(1)
Figure 2-9:
TXCTRLACK<n> and RXCTRLACK<n> at this time refers to all four lanes within the
Quad. The user must wait for all four TXCTRLACK<n> and RXCTRLACK<n> signals
to be deasserted before asserting GTHINIT.
The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than
1 DCLK clock cycle.
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USER_TXRATE
USER_SAMPLERATE
2'b10
Virtex-6 FPGA GTH Transceivers User Guide
2'b00
USER_RXRATE
2'b00
UG371_c2_06_082609
UG371 (v2.0) February 16, 2010