Xilinx Virtex-6 FPGA User Manual page 131

A data width converter block is included in the receive datapath. This block includes:
•
•
•
The PCS_MODE_LANE<n>[7:4] attribute configures the internal data width, and the
RX_FABRIC_WIDTH<n> attribute configures the external data width.
how the interface width for the TX datapath is selected.
Table 4-20: FPGA RX Interface Datapath Configuration
Internal PCS
RX Data Mode
Data Width
8B/10B
64B/66B
Raw
Figure 3-1, page 77
the different modes and the data converter block.
There are certain restrictions that the user must consider when configuring the fabric data
width:
•
•
•
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
A clock generator that takes the internal PCS clock, derived from the recovered clock,
and generates RXUSERCLKOUT to the FPGA logic based on the external data width
selected
A four-byte-deep FIFO that handles the phase difference between the internal PCS
clock and the external user clock
A data width converter between the internal PCS data interface and the external data
interface to the FPGA logic
Fabric Interface
Data Width
20 bits 16 bits
20 bits 32 bits
20 bits 64 bits
64 bits 64 bits
16 bits 16 bits
16 bits 32 bits
16 bits 64 bits
20 bits 20 bits
20 bits 40 bits
20 bits 80 bits
is a block diagram of the PCS logic. It shows the receive datapath with
The fabric interface data width must be the same for both the transmitter and receiver
within a GTH lane.
The data mode must be the same for both the transmitter and receiver within a GTH
lane.
The data mode must be the same on all four GTH lanes within a Quad.
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PCS_MODE_LANE<n>[7:4]
0111
0111
0111
0001
1010
1010
1010
1011
1011
1011
FPGA RX Interface
Table 4-20 shows
RX_FABRIC_WIDTH<n>
16
32
64
6466
16
32
64
20
40
80
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