Enabling Raw Mode; Using The Barrel Shifter - Xilinx Virtex-6 FPGA User Manual

Table 4-14
Table 4-14: RX Raw Mode Read-only Registers
Read-only Registers
RAW_SHIFT_MON_LANE0
RAW_SHIFT_MON_LANE1
RAW_SHIFT_MON_LANE2
RAW_SHIFT_MON_LANE3

Enabling Raw Mode

Follow these steps to enable the raw mode in the GTH receiver:
1.
2.

Using the Barrel Shifter

The raw data mode provides control of the raw bit alignment position to the user. The user
must drive RXSLIP port High to advance the bit alignment position. The bit alignment
position starts at 0 upon reset and increments by one bit on every positive edge of RXSLIP.
The bit alignment position of the barrel shifter can be monitored through either the DRP
interface or the management interface by accessing the
RAW_SHIFT_MON_LANE<n>[4:0] register:
•
•
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
defines the RX raw mode read-only registers.
Type
16-bit Hex This register is used for the barrel shifter from the raw data mode.
[15:5]: Reserved.
[4:0]: Bit position of the LSB of RX data in the serial-to-parallel data
stream.
If the receive fabric data width is configured to 16 bits, 32 bits, or 64 bits:
a. Set PCS_MODE_LANE<n>[7:4] to 4'b1010.
b. Set PCS_RESET_LANE<n> to 0xFF3B.
c. Set PCS_RESET_1_LANE<n>[1:0] to 2'b00.
d. Set RX_FABRIC_WIDTH<n> to "16", "32", or "64."
If the receive fabric data width is configured to 20 bits, 40 bits, or 80 bits:
a. Set PCS_MODE_LANE<n>[7:4] to 4'b1011.
b. Set PCS_RESET_LANE<n> to 0xFF3B.
c. Set PCS_RESET_1_LANE<n>[1:0] to 2'b00.
d. Set RX_FABRIC_WIDTH<n> to "20", "40", or "80."
DRP Address
• RAW_SHIFT_MON_LANE0: 0x500E
• RAW_SHIFT_MON_LANE1: 0x510E
• RAW_SHIFT_MON_LANE2: 0x520E
• RAW_SHIFT_MON_LANE3: 0x530E
Management Interface Address: 0x800E with MMD Address 0x03
Use the Lane Address setting to specify which GTH lane to access.
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RX Raw Mode
Description
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