Xilinx Virtex-6 FPGA User Manual page 123

Table 4-15: RX 64B/66B Block Ports (Cont'd)
Port Dir
RXCTRL0[7:0] Out
RXCTRL1[7:0]
RXCTRL2[7:0]
RXCTRL3[7:0]
RXDATA0[63:0] Out
RXDATA1[63:0]
RXDATA2[63:0]
RXDATA3[63:0]
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Clock Domain
RXUSERCLKIN0 These outputs indicate the status of RXDATA<n> or they are used
as an extension of RXDATA<n> depending on the mode selected
RXUSERCLKIN1
in the receive datapath:
RXUSERCLKIN2
8B/10B: These outputs are asserted when RXDATA<n> is an
RXUSERCLKIN3
8B/10B K character.
RXCTRL<n>[7] corresponds to RXDATA<n>[63:56]
RXCTRL<n>[6] corresponds to RXDATA<n>[55:48]
RXCTRL<n>[5] corresponds to RXDATA<n>[47:40]
RXCTRL<n>[4] corresponds to RXDATA<n>[39:32]
RXCTRL<n>[3] corresponds to RXDATA<n>[31:24]
RXCTRL<n>[2] corresponds to RXDATA<n>[23:16]
RXCTRL<n>[1] corresponds to RXDATA<n>[15:8]
RXCTRL<n>[0] corresponds to RXDATA<n>[7:0]
64B/66B: These outputs are 64B/66B control bits.
Raw mode: These outputs are used as part of RXDATA<n>[71:64].
RXUSERCLKIN0 This output bus is the receive data bus of the receive interface to the
FPGA.
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
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RX 64B/66B Block
Description
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