Xilinx Virtex-6 FPGA User Manual page 53

Table 2-7: PLL Ports (Cont'd)
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Port Dir
RXRATE0[1:0] In
RXRATE1[1:0]
RXRATE2[1:0]
RXRATE3[1:0]
SAMPLERATE0[2:0] In
SAMPLERATE1[2:0]
SAMPLERATE2[2:0]
SAMPLERATE3[2:0]
TXCTRLACK0 Out
TXCTRLACK1
TXCTRLACK2
TXCTRLACK3
TXRATE0[1:0] In
TXRATE1[1:0]
TXRATE2[1:0]
TXRATE3[1:0]
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Clock Domain
TXUSERCLKIN0 This control signal specifies the receiver
lane divider values:
TXUSERCLKIN1
00: Full data rate
TXUSERCLKIN2
10: 1/4 data rate
TXUSERCLKIN3
All other encodings are reserved.
This port is active after the TX side
becomes active. TXUSERCLKIN<n>
must be stable to use this port.
This port must always be set to 2'b00
during initialization and when
GTHRESET is asserted.
TXUSERCLKIN0 This control signal specifies the
frequency of the strobe signal relative to
TXUSERCLKIN1
the internal transmitter PCS clock after
TXUSERCLKIN2
the transmitter lane dividers:
TXUSERCLKIN3
000: Full rate
010: 1/4 rate
All other encodings are reserved.
This port must always be set to 3'b000
during initialization and when
GTHRESET is asserted.
TXUSERCLKIN0 Assertion of this acknowledgment
signal indicates completion of a change
TXUSERCLKIN1
event on TXRATE<n>,
TXUSERCLKIN2
SAMPLERATE<n>, and
TXUSERCLKIN3
TXPOWERDOWN<n>.
The state of this port is valid only after
GTHINITDONE is driven High and
TXUSERCLKIN<n> is stable.
This port is not asserted until all internal
clocks for the TX datapath, including the
PLL output clock, are stable.
TXUSERCLKIN0 This control signal specifies the
transmitter lane divider values:
TXUSERCLKIN1
00: Full data rate
TXUSERCLKIN2
10: 1/4 data rate
TXUSERCLKIN3
All other encodings are reserved.
This port must always be set to 2'b00
during initialization and when
GTHRESET is asserted.
PLL
Description
53