Xilinx Virtex-6 FPGA User Manual page 61

7.
8.
9.
10. Wait for RXCTRLACK<n> to go High.
11. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for
X-Ref Target - Figure 2-6
S R
T H I N I T D O N E
T X P O W E R D O W N < n > [ 1 : 0 ]
T X B U F R E S E T < n >
T X C T R L A C K < n >
R X P O W E R D O W N < n > [ 1 : 0 ]
R X C T R L A C K < n >
R X B U F R E S E T < n >
Figure 2-6: GTH Transceiver Initialization when in Full Line Rate Mode
Note relevant to
1.
Figure 2-7
configuration when the GTH transceiver is configured in divided line rate mode (i.e.,
TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to non-zero
values).
Follow these steps to initialize the GTH transceiver, when configured in divided line rate
mode:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.
11. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.
Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.
Change RXPOWERDOWN<n>[1:0] to 2'b00.
normal operation.
2 Õ b 1 0
2 Õ b 1 0
Figure 2-6:
The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than
1 DCLK clock cycle.
shows the initialization sequence of the GTH Quad following completion of
Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath
mode used in the application for RX and TX, respectively.
Set PCS_RESET_LANE<n> to the datapath mode used in the application.
Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.
Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.
Set TXRATE<n>[1:0] and RXRATE<n>[1:0] to 2'b00, and set SAMPLERATE<n>[2:0]
to 3'b000.
After completion of configuration (GSR going High), wait for GTHINITDONE to go
High. The PLL is locked after GTHINITDONE is asserted.
Change TXRATE<n>[1:0] to the value used for the application and wait for
TXCTRLACK to go High.
Change SAMPLERATE<n>[2:0] to the value used for the application and wait for
TXCTRLACK to go High.
Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.
www.xilinx.com
Reset and Initialization
2 Õ b 0 0
2 Õ b 0 0
U 3 7 1 _ c 2 _ 0 3 _ 0 8 0 7 0 9
61